Package: dlhdl
Configure deployment workflow for deep learning neural network
Use the dlhdl.Workflow object to set options for compiling and deploying your deep learning network to a target FPGA. You create an object of the dlhdl.Workflow class for the specified deep learning network and FPGA bitstream. Use the object to:
Compile the deep learning network.
Estimate the speed and throughput of your network on the specified FPGA device.
Compile and deploy the neural network onto the FPGA.
Predict the class of input images.
Profile the results for the specified network and the FPGA.
dlhdl.Workflow creates a workflow configuration object for you to specify the workflow to deploy your trained series network.
dlhdl.Workflow (Name,Value) creates a workflow configuration object for you to specify the workflow to deploy your trained deep learning network, with additional options specified by one or more name-value pair arguments.
Name of the FPGA bitstream, specified as a character vector. Make sure that the bitstream name matches the data type and the FPGA board that you are targeting. For a list of provided bitstream names, see Use Deep Learning on FPGA Bitstreams.
Example: 'Bitstream', 'arria10soc_single' specifies that you want to deploy the trained network with single data types to an Arria10 SoC board.
Example:'Bitstream','myfile.bit' specifies that you want to deploy the trained network using your custom bitstream file myfile.bit which is in your current working directory.
Example:'Bitstream','C:\myfolder\myfile.bit' specifies that you want to deploy the trained network using your custom bitstream file myfile.bit that is located in the folder 'C:\myFolder'.
Deep learning network name specified as a variable
Example: 'network', snet creates a workflow object for the saved pretrained network, snet. To specify snet, you can import any of the existing supported pretrained networks or use transfer learning to adapt the network to your problem. For information on supported networks, see Supported Pretrained Networks.
Example: 'network', dlquantizeObj creates a workflow object for the quantized network object, dlquantizeObj. To specify dlquantizeObj, you can import any of the supported existing pretrained networks and create an object using the dlquantizer class. For information on supported networks, see Supported Pretrained Networks.
Assign VGG-19 to snet:
snet = vgg19;
'ProcessorConfig' — Optional arguments when estimating workflow object without a bitstreamProcessorConfig (default) | dlhdl.ProcessorConfigCustom processor configuration object specified as dlhdl.ProcessorConfig object
Example: 'ProcessorConfig',hPC
hPC = dlhdl.ProcessorConfig()
hW = dlhdl.Workflow('network', alexnet,'ProcessorConfig',hPC);
'Target' — dlhdl.Target object to deploy network and bitstream to the target devicehTargetTarget object specified as dlhdl.Target object
Example: 'Target',hTarget
hTarget = dlhdl.Target('Intel','Interface','JTAG')
hW = dlhdl.Workflow('network', snet,'Bitstream','arria10soc_single','Target',hTarget);
snet = vgg19;
hW = dlhdl.Workflow('Network',snet,'Bitstream','arria10soc_single', 'Target', hTarget');
snet = vgg19;
hW = dlhdl.Workflow('Network',snet,'Bitstream','myfile.bit', 'Target', hTarget);
snet = getLogoNetwork();
dlquantObj = dlquantizer(snet,'ExecutionEnvironment','FPGA');
Image = imageDatastore('heineken.png','Labels','Heineken');
dlquantizeObj.calibrate(Image);
hTarget = dlhdl.Target('Xilinx','Interface','Ethernet');
hW = dlhdl.Workflow('Network',dlquantizeObj,'Bitstream','zcu102_int8','Target',hTarget);
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